FabTime Wafer Fab Cycle Time Bibliography

We have collected this list of nearly 100 articles related to wafer fab cycle time. Some are application papers, while others are more theoretical, but they all include cycle time as a performance metric. We welcome suggestions for additional papers that fit with this focus. Please use the feedback form on our contact FabTime page.

M. Adams and B. Smoak, “Managing Manufacturing Improvement Using Computer Integrated Manufacturing Methods,” Proceedings of the IEEE/SEMI International Semiconductor Manufacturing Science Symposium - ISMSS '90, 9-13, 1990.

E. Akcali, K. Nemoto, and R. Uzsoy, “Cycle-Time Improvements for Photolithography Process in Semiconductor Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 14, No. 1, 48-56, 2001.

T. Arzt, “Using AutoSched to Optimize the Production Performance of a New Semiconductor Wafer Fab,” Semiconductor Fabtech, Eighth Edition, ICG Publishing, 1998.

T. Arzt and F. Bulcke, “A New Low Cost Approach in 200 mm and 300 mm AMHS,” Semiconductor Fabtech, Tenth Edition, ICG Publishing, 1999.

N. Bahaji, “Simulation Study of the Effect of Dispatching Rules and Lot Release Strategies in Semiconductor Fabrication Facilities,” Master’s Thesis, Louisiana State University and Agricultural and Mechanical College, Department of Industrial and Manufacturing Systems Engineering, December 2000.

R. J. Baseman, W. Grey, S. J. Hood, C. A. Kovac, and R. C. Brilla, “Cycle Time Driven Inventory Cost Analysis,” Proceedings of the IBM International Manufacturing Productivity Symposium, IBM East Fishkill, New York, October 12-15, 1993.

S. M. Berlow, S. J. Hood, and C. Y. Wong, “On Improving Semiconductor Line Cycle Time without Losing Throughput,” Proceedings of the IBM International Manufacturing Productivity Symposium, IBM East Fishkill, New York, October 12-15, 1993.

F. G. Boebel and O. Ruelle, “Cycle Time Reduction Program at ACL,” Proceedings of the 1996 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Cambridge, MA, 165-168, 1996.

J. Bonal, M. Fernadez, O. Maire-Richar, S. Aparicio, R. Oliva, S. Garcia, B. Gonzalez, L. Rodriguez, M. Rosendo, J.C. Villacieros, and J.Becerro, “A Statistical Approach To Cycle Time Management,” Proceedings of the 2001 Advanced Semiconductor Manufacturing Conference (ASMC 01), Munich, Germany, 2001.

J. Bonal, L. Rios, C. Ortega, S. Aparicio, M. Fernandez, M. Rosendo, A. Sanchez, and S. Malvar, “Productivity Improvement Through Cycle Time Analysis,” Working Paper, Lucent Technologies, Madrid, 1996.

J. Bonal, A. Sadai, C. Ortega, S. Aparicio, M. Fernandez, R. Oliva, L. Rodriguez, M. Rosendo, A. Sanchez, E. Paule, and D. Ojeda, “Management of Multiple-Pass Constraints,” Proceedings of the 1998 Advanced Semiconductor Manufacturing Conference (ASMC98), 1998.

A. M. Bonvik, “Estimating the Lead Time Distribution of Priority Lots in a Semiconductor Factory,” Working Paper from Operations Research Center, Massachusetts Institute of Technology, 1-26, 1994.

S. Brown, J. Domaschke, and F. Leibl, “Cycle Time Reductions for Test Area Bottleneck Equipment,” Proceedings of the Second Annual SEMI Test, Assembly, and Packaging Automation and Integration Conference, B1-B5, 1998.

A. W. Chan, A. Satir, and V. J. Thomson, “Reduction of Cycle Time in Manufacturing Using Simulation,” Proceedings of the International Conference on Computer Applications in Production and Engineering (CAPE '97), Detroit, MI, 359-368, November 1997.

F. Chance, J. K. Robinson, J. Fowler, O. Gihr, B. Rodriguez, and L. W. Schruben, “A Design of Experiments Methodology for Semiconductor Wafer Fab Capacity Planning,” SEMATECH Technology Transfer #95062860A-TR, 1995.

P. Chandra and S. Gupta, “Managing Batch Processors to Reduce Lead Time in a Semiconductor Packaging Line,” International Journal of Production Research, Vol. 35, No. 3, 611-633, 1997.

S-C Chang, L-H Lee, L-S Pang, T.W.-Y. Chen, Y-C Weng, H-D Chiang and D.W.-H. Dai, “Iterative Capacity Allocation and Production Flow Estimation for Scheduling Semiconductor Fabrication,” Proceedings of the Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium: Manufacturing Technologies - Present and Future, Austin, TX, 508-512, 1995.

H. Chen, M. Harrison, A. Mandelbaum, A. Van Ackere, and L. Wein, “Empirical Evaluation of A Queueing Network Model for Semiconductor Wafer Fabrication,” Operations Research, Vol. 36, No. 2, 202-215, 1988.

R. Cigolini, A. Comi, A. Micheletti, M. Perona, and A. Portioli, “Implementing New Dispatching Rules at SGS-Thomson Microelectronics,” Production Planning & Control, Vol. 10, No. 1, 97-106, 1999.

D. Connors, G. Feigin, and D. Yao, “A Queueing Network Model for Semiconductor Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 3, 412-427, 1996.

S. P. Cunningham and J. G. Shanthikumar, “Empirical Results on the Relationship Between Die Yield and Cycle Time in Semiconductor Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 2, 73-277, 1996.

W. Danielak and L. Weckwerth, “Increasing Capacity Together With Reducing Cycle Time. A Look at Productivity Improvement Process at GaAs Wafer Fab,” Compound Semiconductor Manufacturing Expo, July 9-11, 2001.

J. E. Dayhoff and R. W. Atherton, “Signature Analysis of Dispatch Schemes in Wafer Fabrication,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-9, No. 4, 518-525, 1987.

L. Demeester and C. S. Tang, “Reducing Cycle Time at an IBM Wafer Fabrication Facility,” Interfaces, Vol. 26, No. 2, 34-49, 1996.

J. Domaschke, S. Brown, and F. Leibl, “No-Cost Applications for Assembly Cycle Time Reduction,” Proceedings of the Semicon West 1998 Technical Symposium on Semiconductor Packaging Technology, July 15-17, 1998, San Jose.

J. Domaschke, S. Brown, J. Robinson, and F. Leibl, “Effective Implementation of Cycle Time Reduction Strategies for Semiconductor Back-End Manufacturing,” Proceedings of the 1998 Winter Simulation Conference, Washington, DC, D. J. Medeiros, E. F. Watson, J. S. Carson, and M. S. Manivannan, eds, 985-992, 1998.

B. Ehteshami, R. G. Petrakian, and P. M. Shabe, “Trade-Offs in Cycle Time Management: Hot Lots,” IEEE Transactions on Semiconductor Manufacturing, Vol. 5, No. 2, 101-105, 1992.

B. L. Farrell, W. Kahan, J. W. Reightler, and A. C. Woodard, “Improving Service Efficiency in Manufacturing Integrated Circuits,” AT&T Technical Journal, 37-44, July/August 1992.

K. Fordyce and G. Sullivan, “Cycle Time Versus Machine Utilization: Moving Along the Curve vs. Shifting the Curve,” IBM Technology Report No. TR 21.1440, 1991.

J. W. Fowler, S. Brown, H. Gold, and A. Schoemig, “Measurable Improvements in Cycle-Time-Constrained Capacity,” Proceedings of the 6th IEEE/UCS/SEMI International Symposium on Semiconductor Manufacturing (ISSM), San Francisco, October 6-8, 1997, A21-A24.

H. Fromm, “Some Remarks on Cycle Time, Variability, Zero Inventories, and Costs in Microelectronics Manufacturing Lines,” IBM Technical Report TR 28.167, 1992.

D. Fronckowiak, A. Peikert, and K. Nishinohara, “Using Discrete Event Simulation to Analyze the Impact of Job Priorities on Cycle Time in Semiconductor Manufacturing,” Proceedings of the 1996 Advanced Semiconductor Manufacturing Conference and Workshop (ASMC 96), Boston, MA, 151-155, 1996.

C. D. Geiger, R. Hase, C. G. Takoudis, and R. Uzsoy, “Alternative Facility Layouts for Semiconductor Wafer Fabrication Facilities,” IEEE Transactions on Components, Packaging, and Manufacturing Technology. Part C: Manufacturing, Vol. 20, No. 2, 152-163, 1997.

N. S. Grewal, A. C. Bruska, T. M. Wulf, and J. K. Robinson, “Integrating Targeted Cycle-Time Reduction into the Capital Planning Process,” Proceedings of the 1998 Winter Simulation Conference, Washington, DC, D. J. Medeiros, E. F. Watson, J. S. Carson, and M. S. Manivannan, eds, 1005-1010, 1998.

N. S. Grewal, A. C. Bruska, T. M. Wulf, and J. K. Robinson, “Validating Simulation Model Cycle Times at Seagate Technology.” In Proceedings of the 1999 Winter Simulation Conference, ed. P. A. Farrington, H. B. Nembhard, D. T. Sturrock, and G. W. Evans, 843-849. Institute of Electrical and Electronics Engineers, Piscataway, New Jersey, 1999.

A. Gupta and K. Potti, “Applications of Simulation Modeling at a Texas Instruments DMOS5 Wafer Fab,” Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM 2002), Editors G. T. Mackulak, J. W. Fowler, and A. Schoemig, Tempe, AZ, April 10-12, 2002. 137-140.

K. Hadavi, M. S. Shahraray, and K. Voigt, “ReDS-A Dynamic Planning, Scheduling, and Control System for Manufacturing,” Journal of Manufacturing Systems, Vol. 9, No. 4, 332-344, 1990.

J. F. Hallas, J. D. Kim, C. Internicola, and C. T. Mosier, “An Investigation of Operating Methods for 0.25 Micron Semiconductor Manufacturing,” Proceedings of the Winter Simulation Conference, 1996.

R. Hase, C. G. Takoudis and R. Uzsoy, “Cellular and Reentrant Layouts for Semiconductor Wafer Fabrication Facilities,” 1994 IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1994.

M. Hillis and J. Robinson, “Extremely Hot Lots: Super-Expediting in a 0.18 Micron Wafer Fab,” Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM 2002), Editors G. T. Mackulak, J. W. Fowler, and A. Schoemig, Tempe, AZ, April 10-12, 2002. 106-111.

G. W. Horn and W. A. Podgorski, “A Focus on Cycle-Time Vs. Tool Utilization "Paradox" with Material Handling Methodology,” Proceedings of the 1998 Advanced Semiconductor Manufacturing Conference and Workshop (ASMC 98), Boston, MA, 405-412, 1998.

Y. F. Hung and R. C. Leachman, “Reduced Simulation Models of Wafer Fabrication Facilities,” International Journal of Production Research, Vol. 37, No. 12, 2685-2701, 1999.

G. Inoue and K. Yoneda, “VLSI Production Analysis Using Queueing Network Model,” Proceedings of the Fifth Symposium on Automated Integrated Circuits Manufacturing, Hollywood, FL, 33-44, 1989.

M. Janakiram, “Cycle Time Reduction at Motorola's ACT Fab,” Proceedings of the 1996 Advanced Semiconductor Manufacturing Conference and Workshop (ASMC 96), Boston, MA, 465-469, 1996.

M. Janakiram and J. R. Morrison, “Capacity Planning and Study of Scheduling Policies Using Simulation at Motorola's Act Fab,” Proceedings of the 1999 SMOMS Conference, San Jose, CA, 1999.

M. D. Jeng, X. L. Xie, and S. W. Chou, “Modeling, Qualitative Analysis, and Performance Evaluation of the Etching Area In An IC Wafer Fabrication System Using Petri Nets,” IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 3, 358-373, 1998.

S. S. Johal, “Non-Linearity and Randomness in a Semiconductor Wafer Fab,” Proceedings of the 1996 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Cambridge, MA, 2-6, 1996.

S. Johal, J. Everton, “Productivity Improvement in a Semiconductor Wafer Fab through Transparent Scheduling Techniques,” Proceedings of the 1997 Advanced Semiconductor Manufacturing Conference and Workshop (ASMC 97), Boston, MA, 201-205, 1997.

Y. D. Kim, D. H. Lee, J. U. Kim, and H. K. Roh, “A Simulation Study On Lot Release Control, Mask Scheduling, And Batch Scheduling In Semiconductor Wafer Fabrication Facilities,” Journal of Manufacturing Systems, Vol. 17, No. 2, 107-117, 1998.

H. Koike, F. Matsuoka, S. Hohkibara, E. Fukuda, K. Tomioka, H. Miyajima, K. Muraoka, N. Hayasaka, and M. Kimura, “Quick-Turnaround-Time Improvement For Product Development And Transfer To Mass Production,” IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 1, 54-62, 1998.

P. Kumar, “Re-Entrant Lines,” Queueing Systems: Theory and Applications: Special Issue on Queueing Networks, Vol. 13, 87-110, 1993.

R. C. Leachman, “Production Planning and Scheduling Practices Across the Semiconductor Industry,” Department of Industrial Engineering and Operations Research, Univ. of California at Berkeley, 1-30, 1994.

R. C. Leachman and D. A. Hodges, “Benchmarking Semiconductor Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 2, 158-169, 1996.

R. C. Leachman, J. Kang, V. Lin, “SLIM: Short Cycle Time and Low Inventory in Manufacturing at Samsung Electronics,” Interfaces, Vol. 32, No 1, 2002.

C.-E. Lee and C.-W. Chen, “A Dispatching Scheme Involving Move Control and Weighted Due Date for Wafer Foundries,” IEEE Transactions on Components, Packaging, and Manufacturing Technology. Part C: Manufacturing, Vol. 20, No. 4, 268-277, 1997.

Y. Lee, S. Kim, S. Yea, and B. Kim, “Production Planning In Semiconductor Wafer Fab Considering Variable Cycle Times,” Computers & Industrial Engineering, Vol. 33, No. 3-4, 713-716, 1997.

G. Leonovich, “An Approach for Optimizing WIP/Cycle Time/Output in a Semiconductor Fabricator,” 1994 IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1994.

S. Li, T. Tang, and D. W. Collins, “Minimum Inventory Variability Schedule with Applications in Semiconductor Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 1, 145-149, 1996.

Y. H. Lin and C. E. Lee, “A WIP Estimation Model for Wafer Fabrication,” International Journal of Industrial Engineering - Theory, Applications and Practice, Vol. 9, No. 3, 222-237, 2002.

M. J. Lopez and S. C. Wood, “Systems of Multiple Cluster Tools: Configuration and Performance under Perfect Reliability,” IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 3, 465-474, 1998.

S. Lou, H. Yan, S. Sethi, A. Gardel, and P. Deosthali, “Using Simulation to Test the Robustness of Various Existing Production Control Policies,” Proceedings of the 1991 Winter Simulation Conference, 261-269, 1991.

S. C. H. Lu, D. Ramaswamy, and P. R. Kumar, “Efficient Scheduling Policies to Reduce Mean and Variance of Cycle-Time in Semiconductor Manufacturing Plants,” IEEE Transactions on Semiconductor Manufacturing, Vol. 7, No. 3, 374-380, 1994.

D. P. Martin, “The Advantages of Using Short Cycle Time Manufacturing (SCM) Instead of Continuous Flow Manufacturing (CFM),” Future Fab International, Volume 9, 1999.

D. F. Martin, “Key Factors in Designing a Manufacturing Line to Maximize Tool Utilization and Minimize Turnaround Time,” IBM Technology Products, Essex Junction, VT, 1994.

L. A. Martin-Vega, M. Pippen, E. Gerdon, and R. Burcham, “Applying Just-In-Time in a Wafer Fab: A Case Study,” IEEE Transactions on Semiconductor Manufacturing, Vol. 2, No. 1, 16-21, 1989.

D. Mercier and O. Bonnin, “300mm Semiconductor Manufacturing Cycle Time Strategy Assessment Through a DOE Based on Dynamic Simulation,” Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM 2002), Editors G. T. Mackulak, J. W. Fowler, and A. Schoemig, Tempe, AZ, April 10-12, 2002. 122-125.

D. J. Miller, “Simulation of a Semiconductor Manufacturing Line,” Communications of the ACM, Vol. 33, No. 10, 98-108, 1990.

S. A. Mosley, T. Teyner, and R. M. Uzsoy, “Maintenance Scheduling And Staffing Policies In A Wafer Fabrication Facility,” IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 2, 316-323, 1998.

A. Najmi, “Management of Cycle Time in Semiconductor Wafer Fabrication,” Engineering Systems Research Center, Report No. 93-3, the University of California at Berkeley, 1993.

A. Najmi and C. Lozinski, “Managing Factory Productivity Using Object-Oriented Simulation for Setting Shift Production Targets in VLSI Manufacturing,” Society of Manufacturing Engineers Technical Paper, AUTOFACT Conference, Detroit, MI, 1989.

S. Nakamura, C. Hashimoto, and O. Mori, “Precise and Flexible Modeling for Semiconductor Wafer Fabrication,” Proceedings of the 1993 Winter Simulation Conference, (eds.) G.W. Evans, M. Mollaghasemi, E. C. Russel, and W.E. Biles, 804-813, 1993.

T. Nakata, K. Matsui, Y. Miyake and K. Nishioka, “Dynamic Bottleneck Control In Wide Variety Production Factory,” IEEE Transactions on Semiconductor Manufacturing, Vol. 12, No. 3, 273-280, 1999.

Y. Narahari and L. M. Khan, “Modeling the Effect of Hot Lots in Semiconductor Manufacturing Systems,” IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No. 1,185-188, 1997.

Y. Narahari and L. M. Khan, “Modeling Re-Entrant Manufacturing Systems With Inspections,” Journal of Manufacturing Systems, Vol. 15, No. 6, 367-378, 1996.

E. Neacy, N. Abt, S. Brown, M. McDavid, J. Robinson, S. Srodes, and T. Stanley, “Cost Analysis for a Multiple Product / Multiple Process Factory: Application of SEMATECH's Future Factory Design Methodology,” Proceedings of the Advanced Semiconductor Manufacturing Conference, Boston, MA, 1993.

K. Nemoto, E. Akcali, and R. Uzsoy, “Quantifying the Benefits of Cycle Time Reduction in Semiconductor Wafer Fabrication,” IEEE Transactions on Electronics Packaging Manufacturing, Vol. 23, No. 1, 39-47, 2000.

J. M. Neve, F. D. Ray and J. P. Sitarik, “Improving the Performance of an Integrated Circuit Manufacturing Line,” AT&T Technical Journal, Vol. 66, No. 5, 39-48, 1987.

D. S. O’Ferrell, “Manufacturing Modeling and Optimization,” Proceedings of the IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 334-339, 1995.

P. O’Neil, “Performance Evaluation of Lot Dispatching and Scheduling Algorithms Through Discrete Event Simulation,” Proceedings of the 3rd International Semiconductor Manufacturing Science Symposium, Burlington, CA, 21-24, 1991.

C. Ortega, J. Bonal, and J. C. Collado, “Effect of Cycle Time and Fab Yield Variation on the Number of Wafer Outs Variability: A Monte Carlo Case Study,” Proceedings of the SPIE - The International Society for Optical Engineering, Vol. 32, No. 16, 82-87, 1997.

S. Pampel, J. Domaschke, and H. Jetter, “Productivity improvement for dry etch equipment through the application of simulation,” Proceeding of the 2000 International Symposium on Semiconductor Manufacturing (ISSM 2000), 2000.

A. Peikert and S. Brown, “A Rapid Modeling Technique for Measurable Improvements in Factory Performance,” Proceedings of the 1998 Winter Simulation Conference, Washington, DC, D. J. Medeiros, E. F. Watson, J. S. Carson, and M. S. Manivannan, eds., 1011-1015, 1998.

T. L. Perkinson, R. S. Gyurcsik, and P. K. McLarty, “Single-Wafer Cluster Tool Performance: An Analysis of the Effects of Redundant Chambers and Revisitation Sequences on Throughput,” IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 3, 384-400, 1996.

K. Potti and S. J. Mason, “Using Simulation to Improve Semiconductor Manufacturing,” Semiconductor International, 289-292, July 1997.

A. Raddon and B. Grigsby, “Throughput Time Forecasting Model,” Proceedings of the 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 430-433, 1997.

U. Rohrer, “Automated Lot Tracking and Identification System,” Proceedings of the 1998 Advanced Semiconductor Manufacturing Conference and Workshop (ASMC 98), Boston, MA, 142-144, 1998.

R. Sandell, “Scheduling Policies in Semiconductor Manufacturing Systems,” SEMATECH Technology Transfer # 95062884A-XFR, July 31, 1995.

L. Sattler, “Using Queueing Curve Approximations in a Fab to Determine Productivity Improvements,” Proceedings of the 1996 Advanced Semiconductor Manufacturing Conference and Workshop (ASMC 96), Boston, MA, 140-145, 1996.

L. Sattler, S. O'Connor, M. Hallinan and T. Finucane, “Techniques for Analyzing Cycle Time Variability in Fab and Probe,” Proceedings of the 1999 Advanced Semiconductor Manufacturing Conference (ASMC), Boston, MA, 1999.

S. Simmons, “Modeling Yield Throughout the DRAM Product Life Cycle,” Proceedings of the 1999 International Symposium on Semiconductor Manufacturing (ISSM '99), 1999.

A. M. Spence and D. J. Welter, “Capacity Planning of a Photolithography Work Cell in a Wafer Manufacturing Line,” Proceedings of the IEEE International Conference on Robotics and Automation, Raleigh, NC, 702-708, 1987.

K. Srinivasan, R. Sandell, and S. Brown, “Correlation Between Yield And Waiting Time: A Quantitative Study,” Proceedings of the Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium: Manufacturing Technologies - Present and Future, Austin, TX, 65-69, 1995.

G. Sullivan and K. Fordyce, “IBM Burlington's Logistics Management System,” Interfaces, Vol. 20, No. 1, 43-64, 1990. Updated article available in Production and Operations Management, Vol. 1, No. 1, 70-86, 1992.

W. J. Trybula, “Hot Jobs, Bane or Boon,” Proceedings of the 1993 IEEE/CHMT International Electronics Manufacturing Technology Symposium, Santa Clara, CA, 317-322, 1993. Also available as SEMATECH Technology Transfer No. 93041617A-ER.

B. Tullis, V. Mehrotra, and D. Zuanich, “Successful Modeling of a Semiconductor R&D Facility,” Proceedings of the 1990 IEEE/SEMI International Semiconductor Manufacturing Science Symposium, 26-32, 1990.

L. M. Wein, “On the Relationship Between Yield and Cycle Time in Semiconductor Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 5, No. 2, 156-158, 1992.

L. M. Wein, “Scheduling Semiconductor Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 3, 115-126, 1988.

S. C. Wood, “Cost and Cycle Time Performance of Fabs Based on Integrated Single-Wafer Processing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No. 1, 98-111, 1997.

A. M. Zargar and B. Ehteshami, “Tradeoffs in Cycle Time Management: Reworked Bonus Lots,” Proceedings of the Summer Computer Simulation Conference, 1039-1043, 1991.