FabTime Cycle Time Management for Wafer Fabs
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Cycle Time Reductions for Test Area Bottleneck Equipment

Authors:

Steven Brown
Joerg Domaschke
Siemens AG
Franz Leibl
Siemens Microelectronics Center

Abstract:

Using discrete-event simulation models, a study was conducted to evaluate the current production practices of a high-volume semiconductor assembly and test operation. The specific goal of the study was to find potential areas for productivity improvement that would collectively yield a 60% reduction in manufacturing cycle time for the back-end factory. This paper will present findings and measurable results pertaining to the Burn-In and Tester operations, which are the current factory constraints. The model shows that the cumulative impact of these recommendations is a 32% reduction in average cycle time, a significant contribution to the overall goal. Additional opportunities are being investigated with models of the Assembly area.

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